| 32位单精度浮点乘法器的FPGA实现 |
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| 引用本文： | 胡侨娟,仲顺安,陈越洋,党华.32位单精度浮点乘法器的FPGA实现[J].现代电子技术,2005,28(24):23-24,27. |
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| 作者姓名： | 胡侨娟 仲顺安 陈越洋 党华 |
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| 作者单位： | 北京理工大学,北京,100081 |
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| 摘 要： | 采用Verilog HDL语言,在FPGA上实现了32位单精度浮点乘法器的设计,通过采用改进型Booth算法和Wallace树结构,提高了乘法器的速度.本文使用Altera Quartus II 4.1 仿真软件,采用的器件是EPF10K100EQ240-1,对乘法器进行了波形仿真,并采用0.5 CMOS工艺进行逻辑综合.
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| 关 键 词： | 浮点乘法器 Booth算法 Wallace树 波形仿真 |
| 文章编号： | 1004-373X（2005）24-023-02 |
| 收稿时间： | 2005-08-13 |
| 修稿时间： | 2005-08-13 |
Implementation of 32-bit Single Precision Floating Point Multiplier Based on FPGA |
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| HU Qiaojuan,ZHONG Shunan,CHEN Yueyang,DANG Hua.Implementation of 32-bit Single Precision Floating Point Multiplier Based on FPGA[J].Modern Electronic Technique,2005,28(24):23-24,27. |
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| Authors: | HU Qiaojuan ZHONG Shunan CHEN Yueyang DANG Hua |
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| Institution: | Beijing Institute of Technology,Beijing, 100081 ,China |
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| Abstract: | Using Verilog HDL,a design of 32 b single precision floating point multiplier based on FPGA is presented.By using a structure of Wallace trees and Booth algorithm,the speed of multiplier has been improved.The software of Altera Quartus II 4.1 is used for performing the wave simulation of the multiplier with EPF10K100EQ2401 device.The multiplier is synthesized with 0.5 CMOS technology. |
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| Keywords: | floating point multiplier Booth algorithm Wallace trees wave simulation |
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