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CMOS工艺中NPN bipolar的开发
引用本文:崔金洪.CMOS工艺中NPN bipolar的开发[J].电子与封装,2014(11):34-36.
作者姓名:崔金洪
作者单位:深圳方正微电子有限公司,广东深圳,518116
摘    要:由于技术的迅速发展与突破,使集成电路的制造得以在短短的60年间,单一晶粒已经可以容纳数千万个电晶体的超大型集成电路。其主要工艺为CMOS工艺,原因是它有功耗低、集成度高、噪声低、抗辐射能力强等优点,但是传统bipolar工艺有频率高、功率大的优点,因此提出在CMOS中集成三极管、二极管。论述了在0.5μm CMOS工艺中集成NPN bipolar的方法以及各个关键技术指标的确定。

关 键 词:互补型场效应晶体管  双极  实验设计  击穿电压

The Development of CMOS Technology in NPN Bipolar
CUI Jinhong.The Development of CMOS Technology in NPN Bipolar[J].Electronics & Packaging,2014(11):34-36.
Authors:CUI Jinhong
Institution:CUI Jinhong (Founder Microelectronics International Co., Ltd., Shenzhen 518116, China)
Abstract:Due to the rapid development of growth and breakthrough technology, the manufacture of integrated circuits in a short span of 60 years, single grain can accommodate tens of millions of transistors ultra large integrated circuit, and the main process of the CMOS process, because it has low power consumption, integration high, low noise, the advantages of strong ability of resisting radiation, but the traditional bipolar technology has the advantages of high frequency, power, so want to integration in the CMOS tube triode, diode. The paper discusses the method of integration of NPN bipolar in 0.5 μm CMOS process, the shutdown technology index.
Keywords:CMOS  bipolar  DOE  BV
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