FPGA中的基于ODDR技术的并行采样设计

介绍了一个通过4片250MSps的高速ADC交替采样实现高达1GSps数据采集系统实现方案,对关键部分的采样时钟系统设计进行了重点讨论,详细介绍了基于Spantan-3AFPGAODDR2技术的采样时钟系统实现方法;给出了多通道数据接收和同步的实现方案,对硬件实现的关键点给出了建议和说明;整个系统硬件方案简洁、性能稳定、且实现成本非常低廉;对系统的性能测试表明其有效位数高于6比特,满足实际应用的需求,适合于高速数字信号获取及处理等领域。

Parallel Acquisition Design Based on ODDR in FPGA

This paper describes a high-speed data acquisition,which is accomplished by interleaving sample with four 250MSps ADC,and the sampling rate is high-up 1GSps;The sampling clock system, which is the key point in design,is discussed;the implement method of sampling clock, which is based on the technique of Spantan-3A FPGA ODDR2,was introduced in detail;One receiving and synchroniz- ing method of multiple data channels is given,and the key point of hardware implement is advised;The whole scheme of hardware system is concise and stable,but the cost is very low.The ENOB of this sys- tem is above 6 bit,and meets the demand,this scheme is fit for high-speed digital signal acquisition and processing.