| 3.125Gb/s基于PS/PI型的时钟与数据恢复电路设计 |
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| 引用本文： | 邱旻韠,张长春,李轩,李卫,郭宇锋,方玉明,陈德媛.3.125Gb/s基于PS/PI型的时钟与数据恢复电路设计[J].中国集成电路,2013(5):28-33. |
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| 作者姓名： | 邱旻韠 张长春 李轩 李卫 郭宇锋 方玉明 陈德媛 |
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| 作者单位： | 南京邮电大学电子科学与工程学院,江苏南京210003 |
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| 摘 要： | 基于标准0.18μmCMOS工艺,设计了一种全速率PS/PI型时钟与数据恢复(CDR)电路。该电路主要由bang-bang型鉴相器、数字控制模块、分接器、相位选择器以及相位插值器等模块构成。根据本CDR的特点,提出了一种在分接器后对超前、滞后信息进行统计比较得到一组低速信号来解决高速模拟电路和低速数字电路之间的接口问题。
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| 关 键 词： | 时钟数据恢复 数模混合电路 分接器 相位插值器 |
Design of a 3.125Gb/s PS / PI-based Clock and Data Recovery Circuit |
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| QIU Min-wei,ZHANG Chang-chun,LI Xuan,LI Wei,GUO Yu-feng,FANG Yu-ming,CHEN De-yuan.Design of a 3.125Gb/s PS / PI-based Clock and Data Recovery Circuit[J].China Integrated Circuit,2013(5):28-33. |
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| Authors: | QIU Min-wei ZHANG Chang-chun LI Xuan LI Wei GUO Yu-feng FANG Yu-ming CHEN De-yuan |
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| Institution: | (School of Electronic Science and Engineering, Nanjing University of Posts and Telecommunica-tion, Nanjing, 210003, China) |
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| Abstract: | Based on 0.18umCMOS process, a full rate of PS/PI clock and data recovery （ CDR ） circuit was designed. The circuit mainly consists of a bang-bang phase detector, digital controller, de-multiplexer, phase selector, and phase interpolator. According to the characterist-ics of the CDR, there is proposed a method of comparing the UP and DN information after demultiplexer ,in order to get a batch of speed analog circuit and low speed digital circuit. signals to solve the problem of interface between h-igh |
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| Keywords: | Clock and data recovery Mixed analog-digital circuit Demuhiplexer Phase detector |
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