| 基于VHDL的高可靠性RAM的IP核设计 |
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| 引用本文： | 谈荒,邱跃洪,陈智,李巍.基于VHDL的高可靠性RAM的IP核设计[J].科学技术与工程,2007,7(14):3547-3551. |
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| 作者姓名： | 谈荒 邱跃洪 陈智 李巍 |
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| 作者单位： | 1. 中国科学院研究生院,北京,100039;中国科学院西安光学精密机械研究所,西安,710119
2. 中国科学院西安光学精密机械研究所,西安,710119 |
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| 摘 要： | 设计一个采用扩展Hamming码来纠错的高可靠性RAM的IP核。提出一种充分利用厂商提供的,经过特殊优化的基本宏功能模块来设计RAM的IP核的方案。试验结果证明,该RAMIP核满足设计要求,可以正确的配合CPU执行指令,具备应用价值。
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| 关 键 词： | VHDL 扩展Hamming码 RAM IP核 可靠性 纠错 |
| 文章编号： | 1671-1819(2007)14-3547-05 |
| 修稿时间： | 2007-04-05 |
Design of High-dependability RAM IP Core Based on VHDL |
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| TAN Huang,QIU Yue-hong,CHEN Zhi,LI Wei.Design of High-dependability RAM IP Core Based on VHDL[J].Science Technology and Engineering,2007,7(14):3547-3551. |
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| Authors: | TAN Huang QIU Yue-hong CHEN Zhi LI Wei |
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| Abstract: | An IP core of high- dependability RAM with Extended Hamming Code to correct error was designed and implemented . A design method of RAM with Megafunctions/LPM which had been optimized by the manufacturer was put forward. The final results given by experiments shows that the RAM IP Core fits the parameters of design exactly. The mc8051 IP core runs smoothly with the RAM IP core as its external ram, which shows its practical value. |
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| Keywords: | VHDL extended hamming code RAM IP core dependability error correction |
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