| 高精度ADC转换核的设计 |
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| 引用本文： | 徐新宇,黄昀荃,徐睿.高精度ADC转换核的设计[J].电子与封装,2011,11(8):19-21,48. |
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| 作者姓名： | 徐新宇 黄昀荃 徐睿 |
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| 作者单位： | 中国电子科技集团公司第58研究所,江苏无锡,214035 |
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| 摘 要： | 在DSP的A/D转换电路中,转换核电路是整个电路的核心模块,包括时钟电路、采样保持电路（S/H）、MDAC电路、比较器电路、子ADC译码电路、冗余位数字校正电路等。同时转换核电路通常又是整个A/D电路中功耗最大的模块,其性能直接决定了整个A/D转换器的性能。文章介绍了一种l2位25MS/s转换核电路设计。该电路采用TS...
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| 关 键 词： | 流水线ADC DSP 转换核电路 |
The High Precision of Conversion-core Design in ADC |
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| XU Xin-yu,HUANG Yun-quan,XU Rui.The High Precision of Conversion-core Design in ADC[J].Electronics & Packaging,2011,11(8):19-21,48. |
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| Authors: | XU Xin-yu HUANG Yun-quan XU Rui |
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| Institution: | XU Xin-yu,HUANG Yun-quan,XU Rui(China Electronics Technology Group Corporation No.58th Institute,Wuxi 214035,China) |
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| Abstract: | The conversion core circuit is the hard core in A/D of DSP.It include： CLK,S/H,MDAC,et al.Conversion core circuit also is the largest power consumer in ADC,usually.Its character determines the entire ADC.This paper introduces a 12bit 25MS/s conversion core circuit design.This circuit use 0.18μm CMOS technology,and layout is 1.69mm2.Hspice is used for simulating.The results show that： SFDR is 75dB,SNDR is 60dB,and power is 33.41mW,when the circuit works on 25MS/s,and input signal frequency is 6.5MHz.This work supplies a good technologic base for high precision DSP design. |
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| Keywords: | pipeline ADC DSP conversion core circuit |
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