基于FPGA的高阶全数字锁相环的设计与实现

提出了一种实现高阶全数字锁相环的新方法。该锁相环以数字比例积分控制取代了传统的一些数字环路滤波控制方法，具有电路结构简单、摔制灵活、跟踪精度高、环路性能好和易于集成的特点。文中介绍了该高阶全数字锁相环的系统结构和工作原理，对其性能进行了理论分析和计算机仿真。应用EDA技术设计了该系统，并用FPGA实现了其硬件电路。仿真和硬件测试结果证实了该设计的正确性。

Design and implementation of a high-order all DPLL based on FPGA

A novel design and implementation approach to a high-order all DPLL has been proposed in this paper. In this DPLL a Proportion-Integral(PI) control algorithm based block was substituted for some conventional digital filter based ones. And it is characteristic of its simple structure, flexible control method, high phase tracking precision, excellent loop performance and easy system integration, etc.. At first the system structure and principles of the high-order all DPLL are introduced, then relevant theoretic computation and computer simulation are implemented. At last its FPGA based prototype is developed by using EDA technology. It makes sure from the simulation and experiment results that the design method is correct.