Low-Power High-Performance Asymmetrical Double-Gate Circuits Using Back-Gate-Controlled Wide-Tunable-Range Diode Voltage |
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Authors: | Keunwoo Kim Ching-Te Chuang Kuang JB Ngo HC Nowka KJ |
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Institution: | IBM T. J. Watson Res. Center, Yorktown Heights; |
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Abstract: | This paper presents a new power-reduction scheme using a back-gate-controlled asymmetrical double-gate device with robust data-retention capability for high-performance logic/SRAM power gating or variable/dynamic supply applications. The scheme reduces the transistor count, area, and capacitance in the header/footer device and provides a wide range of virtual ground (GND) or supply voltage. Physical analysis and numerical mix-mode device/circuit-simulation results confirm that the proposed scheme can be applied to low-power high-performance circuit applications in 65-nm technology node and beyond. Variable/dynamic supply or GND voltage using the proposed scheme improves read and write margins in scaled SRAM without degrading read and write performance. |
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