Generation and evaluation of current and logic tests for switch-level sequential circuits |
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Authors: | Chun-Hung Chen Jacob A Abraham |
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Institution: | (1) Computer Engineering Research Center, The University of Texas at Austin, 2201 Donley Dr., Ste. 395, 78758 Austin, TX, USA |
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Abstract: | This article presents an approach to developing high quality tests for switch-level circuits using both current and logic test generation algorithms. Faults that are aborted or undetectable by logic tests may be detected by current tests, or vice versa. An efficient switch level test generation algorithm for generating current and logic tests is introduced. Clear definitions for analyzing the effectiveness of the joint test generation approach are derived. Experimental results are presented for demonstrating high coverage of stuck-at, stuck-on, and stuck-open faults for switch level circuits when both current and logic tests are used.This is expanded version of the work originally presented at the 1991 International Test Conference. |
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Keywords: | Current tests I
DDQ
logic tests test generation |
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