套刻偏差对4H-SiC 浮动结结势垒肖特基二极管的影响研究

4H-SiC浮动结结势垒肖特基二极管与常规结势垒肖特基二极管相比在 相同的导通电阻条件下具有更高的击穿电压. 由p⁺埋层形成的浮动结与主结p⁺区 之间的套刻对准是实现该结构的一项关键技术. 二维模拟软件ISE的模拟结果表明, 套刻偏差的存在会明显影响器件的击穿特性, 随着偏差的增大击穿电压减小. 尽管主结和埋层的交错结构与对准结构具有相似的击穿特性, 但是当正向电压大于2 V后, 交错结构的串联电阻更大.

Study of the effect of lithography deviation on 4H-SiC floating junction junction barrier Schottky diode

The breakdown voltage of 4H-SiC junction barrier schottky diode with floating junction is larger than that of traditional junction barrier Schottky diode under the condition of the same fixed on-resistance. It is a crucial technology that the alignment of lithography between p⁺ region of floating junction and main junction. The simulation results obtained using two-dimensional simulator ISE show that the breakdown voltage obviously drops with the deviation of lithography increasing. Although the breakdown characteristics of the dislocation and the alignment structure are similar, the series resistance of the dislocation structure is larger than the latter when the forward voltage is larger than 2 V.