U型槽刻蚀工艺对GaN垂直沟槽型金属-氧化物-半导体场效应晶体管电学特性的影响

U型槽的干法刻蚀工艺是GaN垂直沟槽型金属-氧化物-半导体场效应晶体管(MOSFET)器件关键的工艺步骤,干法刻蚀后GaN的侧壁状况直接影响GaN MOS结构中的界面态特性和器件的沟道电子输运.本文通过改变感应耦合等离子体干法刻蚀工艺中的射频功率和刻蚀掩模,研究了GaN垂直沟槽型MOSFET电学特性的工艺依赖性.研究结果表明,适当降低射频功率,在保证侧壁陡直的前提下可以改善沟道电子迁移率,从35.7 cm^2/(V·s)提高到48.1 cm^2/(V·s),并提高器件的工作电流.沟道处的界面态密度可以通过亚阈值摆幅提取,射频功率在50 W时界面态密度降低到1.90×10^12 cm^-2·eV^-1,比135 W条件下降低了一半.采用SiO2硬刻蚀掩模代替光刻胶掩模可以提高沟槽底部的刻蚀均匀性.较薄的SiO2掩模具有更小的侧壁面积,高能离子的反射作用更弱,过刻蚀现象明显改善,制备出的GaN垂直沟槽型MOSFET沟道场效应迁移率更高,界面态密度更低.

Effect of U-shape trench etching process on electrical properties of GaN vertical trench metal-oxidesemiconductor field-effect transistor

As reported by several market analysts,GaN-based power devices show great potential applications in the low and medium voltage range(<900 V).For high voltage(>1200 V),including ship transportation and power grid,the future applications of GaN highly depend on the development of vertical devices based on GaN substrates.Several vertical devices have been reported,such as current aperture vertical electron transistors(CAVETs),U-shape trench metal-oxide-semiconductor field-effect transistors(UMOSFETs),and fin power transistors.And the UMOSFETs show potential advantages due to greater simplicity in material epitaxy and fabrication process.In the fabrication of UMOSFETs,the U-shape trench dry etching is the most critical process.The GaN sidewalls after dry etching directly affect the interface state characteristics in the MOS structure and the channel electron transport.In this work,etching optimization including etching radiofrequency(RF)power and etching mask is investigated and process-dependent electrical characteristics of GaN UMOSFETs are also studied.The appropriate decrease of RF power ensuring the steep sidewalls can effectively improve the channel electron mobility from 35.7 cm^2/(V·s)to 48.1 cm^2/(V·s)and consequently increase the ONstate current and reduce the ON-state resistance.Larger etching damage to the p-GaN sidewall caused by higher RF power leads the scattering effects to increase and the mobility of the channel carriers to decrease.The interface state density at the channel can be extracted by the subthreshold swing.The interface state density decreases to 1.90×10^12 cm^-2·eV^-1 when the RF power is regulated to 50 W,which is only half of the interface state density when RF power is 135 W.Similar breakdown voltages(350-380 V)are measured for these devices with varying RF power,which are governed by gate early breakdown.Positive valence band offset is formed in the SiO2/GaN MOS structure and the early breakdown occurs due to the holes accumulating at the SiO2/GaN interface.The etching uniformity at the bottom of U-shape trench can be improved by using the SiO2 hard masks instead of photoresist masks.Sub-trenches at both ends of the trench bottom are observed in the device with photoresist masks,leading the carrier scattering to increase and ON-state current to decrease.Besides,the interface state density decreases from 3.42×10^12 cm^-2·eV^-1 to 2.46×10^12 cm^-2·eV^-1 with a SiO2 hard mask layer used.Compared with 1.6μm photoresist mask,the thinner SiO2 mask with a thickness of 500 nm has a small sidewall area,which weakens the high-energy ion reflection in the inductively coupled plasma system.Consequently,the over-etching at the bottom ends of the trench is improved significantly and therefore the fabricated GaN UMOSFET has higher channel mobility and a lower interface state density.