New traffic model for performance analysis of processor-memory multistage interconnection networks |
| |
| Authors: | Edirisooriya S Edirisooriya G |
| |
| Institution: | Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA; |
| |
| Abstract: | Multistage interconnection networks (MINs) provide cost effective, high bandwidth processor-memory communication in multiprocessor systems. The authors propose a nonuniform traffic model to analyse performance of processor-memory MINs, in the presence of switch and link failures.<> |
| |
| Keywords: | |
|
|
