Single-electron transistors fabricated with sidewall spacer patterning |
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Authors: | Byung-Gook Park Dae Hwan Kim Kyung Rok Kim Ki-Whan Song Jong Duk Lee |
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Affiliation: | Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Republic of Korea |
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Abstract: | We have implemented a sidewall spacer patterning method for novel dual-gate single-electron transistor (DGSET) and metal–oxide–semiconductor-based SET (MOSET) based on the uniform SOI wire, using conventional lithography and processing technology. A 30 nm wide silicon quantum wire is defined by a sidewall spacer patterning method, and depletion gates for two tunnel junctions of the DGSET are formed by the doped polycrystalline silicon sidewall. The fabricated DGSET and MOSET show clear single-electron tunneling phenomena at liquid nitrogen temperature and insensitivity of the Coulomb oscillation period to gate bias conditions. On the basis of the phase control capability of the sidewall depletion gates, we have proposed a complementary self-biasing method, which enables the SET/CMOS hybrid multi-valued logic (MVL) to operate perfectly well at high temperature, where the peak-to-valley current ratio of Coulomb oscillation severely decreases. The suggested scheme is evaluated by SPICE simulation with an analytical DGSET model, and it is confirmed that even DGSETs with a large Si island can be utilized efficiently in the multi-valued logic. |
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Keywords: | Sidewall spacer patterning Single-electron transistor DGSET MOSET Phase control Sidewall depletion gate Multi-valued logic Complementary self-biasing method SPICE |
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