基于多阈值技术的低功耗D触发器设计

目前CMOS电路中,漏电流功耗已经成为不可忽视的部分.降低电路漏电流功耗的一种有效方法是采用多阈值电路技术.根据多阈值电路设计原理,电路的关键路径采用低阈值晶体管,以保证电路的性能;非关键路径采用高阈值晶体管,以降低电路的漏电流功耗.对于触发器来说,其对时钟的响应部分是一个关键路径,而对信号的响应部分是非关键路径.本文据此设计了一种新型低功耗D触发器--多阈值与非门保持型D触发器.该电路结构简单,降低了电路漏电流功耗,并且当输入保持不变时,时钟信号不作用于内部结点,使内部结点电压保持不变,这进一步降低了电路的功耗.模拟结果表明所设计的D触发器跟传统的D触发器相比,可节省近25%的功耗.

Design of low-power D-flip-flop based on multithreshold technique

In present CMOS circuits, the power dissipation caused by leakage current can not be neglected anymore. An effective way to reduce the leakage power is by means of multithreshold technique. According to the principle of multithreshold, low-V-{th} transistors are assigned to critical paths of the circuit to enhance its performance, while high-V-{th} transistors are assigned to non-critical paths to reduce its leakage current. For the Flip-flop, the part responding to clock is the critical path, another part responding to signal is the non-critical path, thereby a new D-FF--Multi-Threshold Nand Keeper D Flip-flop (MT-NKDFF) is designed. MT-NKDFF is simple, and reduces the leakage power. When the inputs to MT-NKDFF are unaltered, the clock signal can't be effective on its internal nodes, so the voltage of the nodes wouldn't change, which decreases the power dissipation of the whole circuit. The results of simulations suggest that the designed MT-NKDFF saves about 25% power compared with conventional D-FF.