基于FPGA的PLC并行执行定时器/计数器的设计

针对ARM+FPGA构建的PLC系统,分析PLC对定时器/计数器的功能需求,设计了可以并行执行的定时器/计数器,构建的定时器/计数器共用一个端口读写控制器与FPGA中央控制器进行数据通信,定时器/计数器内部工作是相互独立的,能够并行的工作,并通过使用地址映射存储器使得定时器/计数器的指令执行更加高效。对中央控制器与定时器/计数器的通信时序和通信格式进行了设计,方便了中央控制器对定时器/计数器的控制与测试。通过仿真测试,该定时器/计数器能够满足PLC定时器/计数器的基本功能,并且达到了稳定的定时/计数的设计要求。

Design of Parallel Operated Timer /Counter in PLC Based on FPGA

PLC system based on Arm and FPGA construction, analysis the functional requirements of the PLC to the timer / counter, design can be executed in parallel timer / counter, construct the timer / counter. And shared with a single port read write data communication controller and FPGA as the central controller, timer / counter for internal work is independent of each other, parallel work. And through the timer / counter instruction operation more efficient by the use of memory address mapping. The communication between the central controller and timer / counter is designed, and the control and testing of the timer / counter is convenient. Through the simulation test, the timer / counter can satisfy the basic function of PLC timer / counter, and achieve the design requirements of the stability of timing / counting.