Charging/discharging kinetics in LPCVD silicon nanocrystal MOS memory structures

The paper focuses on the peculiarities of charging/discharging kinetics and write/erase (W/E) window formation in nanocrystal metal-oxide semiconductor (MOS) non-volatile memory (NVM) structures prepared by low-pressure chemical vapor deposition (LPCVD) of amorphous silicon, followed by solid phase crystallization and thermal oxidation. It is generally known that the W/E window formation via pulse injection depends on the kinetics of carriers trapping (electrons and/or holes) in the nanocrystal NVM structure and consequently on the cumulative time of recharging bias application, i.e. pulse duration and number of applied pulses. In this work, we have shown that with the same cumulative time biasing but different charging pulse durations, the resulting W/E window width can be rather different, demonstrating a staircase window formation. This phenomenon is interpreted by a model of partial fast charge draining from the trapping sites in the vicinity of Si nanoclusters into the Si substrate. The detailed experimental investigation of charging/discharging kinetics of the considered structures in combination with computer simulations lead to the conclusion that there is a single process of negative charge trapping with a time constant of 235±35 ms and at least four processes of positive charge trapping with time constants distributed in the range from <10 ms to >10 s.