| 一种用于数字集成系统的新型CMOS三态缓冲器的设计 |
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| 引用本文： | 彭科, 杨海钢,.一种用于数字集成系统的新型CMOS三态缓冲器的设计[J].电子器件,2007,30(6):2080-2083. |
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| 作者姓名： | 彭科 杨海钢 |
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| 作者单位： | 1. 中国科学院电子学研究所传感技术国家重点实验室,北京,100080;中国科学院研究生院,北京,100039
2. 中国科学院电子学研究所传感技术国家重点实验室,北京,100080 |
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| 摘 要： | 三态逻辑电路已被广泛应用于VLSI数字集成系统中.现在也有很多种实现三态逻辑的方法,但它们要么输出驱动能力不足够强要么占有较大的器件面积.在研究传统三态缓冲器的基础上设计了一种新型的三态缓冲器,据我们所知,这是使用晶体管数目最少的一种三态缓冲器结构.通过SPICE仿真实验表明,所设计的三态缓冲器与传统三态缓冲器相比具有更优的面积-延时积特性和更低的静态功耗.
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| 关 键 词： | VLSI CMOS 三态缓冲 面积-延时积 |
| 文章编号： | 1005-9490(2007)06-2080-04 |
| 修稿时间： | 2007年1月29日 |
Design of A Novel CMOS Three-State Buffer for Digital Integrated Systems |
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| PENG Ke,YANG Hai-gang.Design of A Novel CMOS Three-State Buffer for Digital Integrated Systems[J].Journal of Electron Devices,2007,30(6):2080-2083. |
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| Authors: | PENG Ke YANG Hai-gang |
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| Institution: | 1.The State Key Lab of Transducer Technology; Institute of Electronics; CAS; Beijing 100080; China; 2.Graduate University of the Chinese Academy of Sciences; Beijing 100039; China |
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| Abstract: | The three-state logic is widely used in VLSI digital systems. There are many ways for realization of the CMOS three-state circuit. But they either take too much area or lack of the drive strength. A novel CMOS three-state buffer is proposed based on the research into traditional three-state buffers. To the best of our knowledge, this is a three-state buffer with minimum number of transistors. SPICE simulation demonstrates that the proposed three-state buffer presents optimum area-delay product characteristic and lower static power dissipation compared with other traditional ones. |
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| Keywords: | VLSI CMOS Three-State Area-Delay Product |
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