高速时钟电路设计

在当今的电子设计中，系统越来越复杂，工作频率越来越高，时钟子系统是关于整个系统成败的关键．因此，如何设计出一个高效、高稳定性的时钟子系统成为摆在工程师面前一个头等重要的问题．文章通过分析3种时钟信号的抖动现象(Cycle—Cycle．Jitter、Period Jitter、Long—term Jitter)，针对其产生的原因，提出高速时钟电路设计的解决方案，并结合实际情况给出布线模型．

Design of high speed clock circuit

In modern electrical design, the system becomes more and more complex,and working frequency becomes higher,so clock subsystem is the key to the success of the whole system. Therefore, how to design a high efficient and high stable clock subsystem is a significant problem . Through analysing the Jitter of three kinds of clock signals,it Cycle-Cycle Jitter,Period Jitter and Long-term Jitter,a scheme was proposed for high speed clock circuit design ,and a layout model was put forward according to practical conditions .