| 基于快速舍入的双精度浮点乘法器的设计 |
| |
| 引用本文： | 刘鸿瑾,张铁军,侯朝焕.基于快速舍入的双精度浮点乘法器的设计[J].微电子学与计算机,2006,23(6):162-165. |
| |
| 作者姓名： | 刘鸿瑾 张铁军 侯朝焕 |
| |
| 作者单位： | 中国科学院声学研究所,北京,100080 |
| |
| 摘 要： | 文章设计了一个基于快速合入的双精度浮点乘法器。它通过预测和选择实现快速舍入。克服了传统合入方法舍入模式单一、舍入逻辑复杂、硬件开销大等不足，显著地提高了浮点乘法器的性能。该浮点乘法器采用四级流水线，在0．180μm CMOS工艺下综合实现，关键路径延迟为3．15ns。
|
| 关 键 词： | 浮点乘法 乘法器 快速舍入 |
| 文章编号： | 1000-7180（2006）06-162-04 |
| 收稿时间： | 2005-07-27 |
| 修稿时间： | 2005年7月27日 |
A Double Precision Floating-Point Multiplier with Fast Rounding Method |
| |
| LIU Hong-jin,ZHANG Tie-jun,HOU Chao-huan.A Double Precision Floating-Point Multiplier with Fast Rounding Method[J].Microelectronics & Computer,2006,23(6):162-165. |
| |
| Authors: | LIU Hong-jin ZHANG Tie-jun HOU Chao-huan |
| |
| Institution: | Institute of Acoustics, The Chinese Academy of Sciences, Beijing 100080 |
| |
| Abstract: | A double-precision Floating-point multiplier with fast rounding method is presented in the paper. The method can overcome the disadvantages of the conventional rounding method such as the simple RN rounding mode, complicated rounding logic and large hardware consumption, and can optimize the performance of the multiplier greatly through prediction and selection of the rounding digits. The delay of the critical path is 3.15ns when the multiplier is divided into 4-stage pipeline and implemented with 0.18 um CMOS technology. |
| |
| Keywords: | Floating-point Multiplier Fast rounding |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
