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Jitter tolerance calibration for high-speed serial interfaces |
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| Institution: | 1. Electronics Laboratory, Physics Department, University of Patras, Patras, 26504,Greece;2. Department of Electrical Engineering, Technological Educational Institute of Western Greece, Patras, 26334, Greece;1. Bogazici University, Department of Electrical and Electronics Engineering, Turkey;2. Istanbul Technical University, Department of Electrical and Electronics Engineering, Turkey;1. Electrical and Computer Engineering Department, University of Illinois at Urbana-Champaign, Urbana, IL, United States;2. Intel Corporation, Hillsboro, OR, United States |
| Abstract: | A jitter tolerance calibration test bench suitable for high speed serial interfaces (HSSI) using verilog-AMS is proposed in this paper. The jitter tolerance simulation environment can be easily parameterized in order to be compliant to any HSSI standard specification. As an example, the proposed solution is applied for the jitter tolerance simulation and characterization of the most updated M-PHY ver.3 HSSI standard for mobile applications. A comprehensive method for the calculation of the jitter noise frequency ingredients and the calibration of jitter noise sources is also proposed resulting a jitter tolerance mask compliant with the M-PHY ver.3 specifications. Using the proposed implementation the transistor level and behavioral modules co-simulation time could be significantly minimized. |
| Keywords: | High-speed serial interfaces Jitter tolerance simulation M-PHY standard |
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