一个59mW 10位40MHz流水线A/D转换器 |
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引用本文: | 李建,严杰锋,陈俊,张剑云,郭亚炜,沈泊,汤庭鳌.一个59mW 10位40MHz流水线A/D转换器[J].半导体学报,2005,26(7). |
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作者姓名: | 李建 严杰锋 陈俊 张剑云 郭亚炜 沈泊 汤庭鳌 |
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作者单位: | 1. 复旦大学专用集成电路与系统国家重点实验室,上海,200433 2. 上海微科集成电路有限公司,上海,200433 |
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基金项目: | 上海市集成电路设计创新项目 |
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摘 要: | 设计了一个工作在3.0V的10位40MHz流水线A/D转换器,采用了时分复用运算放大器,低功耗的增益自举telescopic运放,低功耗动态比较器,器件尺寸逐级减小优化功耗.在40MHz的采样时钟,0.5MHz的输入信号的情况下测试,可获得8.1位有效精度,最大积分非线性为2.2LSB,最大微分非线性为0.85LSB,电路用0.25μm CMOS工艺实现,面积为1.24mm2,功耗仅为59mW,其中同时包括为A/D转换器提供基准电压和电流的一个带隙基准源和缓冲电路.
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关 键 词: | 模数转换器 低功耗 共享运算放大器技术 |
A 59mW 10b 40Msample/s Pipelined ADC |
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Abstract: | This paper describes a 3.0V, 10b,40Msample/s analog-to-digital converter (ADC) fabricated in a 0. 25μm CMOS technology. Through the sharing an amplifier between two successive pipeline stages, the converter is realized using just four amplifiers with a separate sample-and-hold block. It employs two key techniques:a high bandwidth low-power gain-boosting telescopic amplifiers technique and a low power low offset dynamic comparators technique.The ADC achieves a 8.1 effective number of bits, a maximum differential nonlinearity of a 0. 85 least significant bit (LSB), and maximum integral nonlinearity of 2.2LSB for a 0.5MHz input at full sampling rate. It occupies 1.24mm2 ,which also includes a bandgap and a voltage reference circuit and dissipates only 59mW. |
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Keywords: | analog-to-digital converter low power OPAMP sharing technique gain-boosting technique |
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