Self-connected horizontal silicon nanowire field effect transistor |
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| Authors: | B Salem F Dhalluin H Abed T Baron P Gentile N Pauc P Ferret |
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| Institution: | 1. Université de Lorraine, Institut Jean Lamour, UMR CNRS 7198, NANCY, F-54042, France;2. Université de Yaoundé 1, Laboratoire de Chimie Minérale, 812 Yaoundé, Cameroun;3. Universidade Federal do Paraná, 81531-990-Curitiba, PR, Brasil;4. CNRS, Institut Jean Lamour, UMR CNRS 7198, NANCY, F-54042, France;1. Peter Grünberg Institut, Electronic Properties (PGI-6), Forschungszentrum Jülich, 52425 Jülich, Germany;2. Fakultät für Physik and Center for Nanointegration Duisburg-Essen (CeNIDE), Universität Duisburg-Essen, 47048 Duisburg, Germany;3. Jülich-Aachen Research Alliance, Fundamentals for Future Information Technology (JARA-FIT), Forschungszentrum Jülich, 52425 Jülich, Germany;1. Dept. of Materials Science and Engineering, Northwestern University, Evanston, IL 60208, United States;2. Dept. of Physics and Astronomy, Northwestern University, Evanston, IL 60208, United States |
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| Abstract: | We propose a technique to fabricate self-connected horizontal Si nanowire (NW) field effect transistors (FETs) by a self-assembly mechanism. We show direct growth of Si NWs between two predefined metallic electrodes along the SiO2 gate oxide using the vapour–liquid–solid (VLS) growth mode. In our approach, the gold catalyst layer is covered by the contact metal, giving rise to selective and localized catalytic activity and growth of NWs from the gold edges. The diameter of the NWs can be adjusted by the thickness of the catalyst layer. Using such a process, we demonstrate field effect operation on the conductivity of a non-intentionally doped 20 nm diameter Si NW. This technique can be implemented in three dimensions, paving the way to three-dimensionalD integration using vertical stacks of self-connected FETs. |
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