循环码计数器的快速综合

本文导出了使用J-K触发器的任意2~n进制循环码计数器激励函数的设计公式,并将逻辑函数修改技术用于任意2N进制循环码计数器的综合。此外,还提出了使用附加触发器时循环码计数器的快速综合法。通过设计实例表明,采用快速综合法设计循环码计数器具有一定的优点和实用意义。

Fast Synthesis of Cyclic-Code Counter

In this paper a formula for the design of an arbitrary modulo-2n counter with cyclic code using J-K flip-flops is derived, and the modification technique of the logic functions is applied to the synthesis of any modulo-2N counter with cyclic code. Furthermore, a fast synthesis for the cyclic-code counter using additional flip-flop is also proposed. Some design examples show that the adoption of the fast synthesis of the cyclic-code counter is of great advantage and practical significance.