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| 基于互补型SET的通用阈值逻辑门设计 | |
| 引用本文： | 应时彦,孔伟名,肖林荣,王伦耀. 基于互补型SET的通用阈值逻辑门设计[J]. 浙江大学学报(理学版), 2017, 44(4): 424-428. DOI: 10.3785/j.issn.1008-9497.2017.04.007 |
| 作者姓名： | 应时彦 孔伟名 肖林荣 王伦耀 |
| 作者单位： | 1. 浙江工业大学 信息工程学院, 浙江 杭州 310023; 2. 嘉兴学院 电子信息工程系, 浙江 嘉兴 314001; 3. 宁波大学 信息科学与工程学院, 浙江 宁波 315211 |
| 基金项目： | 国家自然科学基金资助项目（62471211）；浙江省自然科学基金资助项目（Y1110808）. |
| 摘 要： | 与MOS管相比,单电子晶体管(SET)具有超低功耗、超高集成度等优点,被认为是可能取代MOS管的新一代量子器件的主要竞争者.在简要介绍SET特性及通用阈值逻辑门(UTLG)的基础上,沿用CMOS逻辑电路的设计思想,提出了功能强大的基于互补型SET的三变量UTLG实现方案.利用一个UTLG辅之少量门电路就可实现全部256个三变量逻辑函数.通过实例说明了利用查表设计进行UTLG综合的过程.对所设计的SET电路进行了Pspice仿真,结果表明,基于SET的UTLG以及用UTLG实现的全比较器均具有正确的逻辑功能. |
| 关 键 词： | 单电子晶体管 通用阈值逻辑门 SET电路 电路设计 |
| 收稿时间： | 2016-02-03 |
Design of universal threshold logic gate based on complementary SET |
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| YING Shiyan,KONG Weiming,XIAO Linrong,WANG Lunyao. Design of universal threshold logic gate based on complementary SET[J]. Journal of Zhejiang University(Sciences Edition), 2017, 44(4): 424-428. DOI: 10.3785/j.issn.1008-9497.2017.04.007 | |
| Authors: | YING Shiyan KONG Weiming XIAO Linrong WANG Lunyao |
| Affiliation: | 1. College of Information Engineering, Zhejiang University of Technology, Hangzhou 310023, China; 2. Department of Electronic Information Engineering, Jiaxing University, Jiaxing 314001, Zhejiang Province, China; 3. Faculty of Information Science and Engineering, Ningbo University, Ningbo 315211, Zhejiang Province, China |
| Abstract: | Compared with MOSFET, single electron transistor (SET) has the advantages of ultra-low power consumption and ultra-high integration level, which make it the major candidate for the next generation nano quantum devices. Based on the introduction of SET characteristics and concepts of CMOS logic circuits, a three-variable complementary SET universal threshold logic gate(UTLG)is proposed. All of 256 three-variable logic functions can be realized with a UTLG and only a few logic gates. A full comparator, as an example, is also presented to demonstrate the tabular design procedure of three-variable logic function using a UTLG. The proposed UTLG and SET full comparator are simulated with Pspice and their logic functions are confirmed. |
| Keywords: | single-electron transistor universal threshold logic gates SET circuits circuit design |
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