基于Radix-4 Booth编码的模2n+1乘法器设计

模2n+1乘法(n=8、16)在分组密码算法中比较常见,如IDEA算法,但由于其实现逻辑复杂,往往被视为密码算法性能的瓶颈。提出了一种适用于分组密码算法运算特点的基于Radix-4 Booth编码的模2n+1乘法器实现方法,其输入/输出均无需额外的转换电路,并通过简化部分积生成、采用重新定义的3-2和4-2压缩器等措施以减少路径时延和硬件复杂度。比较其他同类设计,该方法具有较小的面积、时延,可有效提高分组密码算法的加解密性能。

Modulo 2n+1 Multiplier based on Radix-4 Booth Encoding

Modulo 2n+1 multiplication (n=8, 16) is fairly common in block-cipher algorithms, such as IDEA algorithm. However, for its high logic complexity, this multiplication structure is usually regarded as the performance bottleneck of crypto algorithm. A modulo 2n+1 multiplication method suitable for the operation characteristics of block-cipher algorithm based on Radix-4 Booth encoding is thus proposed,and no extra conversion circuits is required in its input and output port, and path delay and hardware complexity are reduced by simplifying partial product, and redefining 3-2 and 4-2 compressor. Compared with other similar implementations, the proposed method enjoys less hardware area and timing delay, and thus could effectively enhances the crypto performances of block-cipher algorithm.