| 一种I2C总线快速收发器设计 |
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| 引用本文： | 杨军,马俊.一种I2C总线快速收发器设计[J].现代电子技术,2006,29(19):37-39. |
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| 作者姓名： | 杨军 马俊 |
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| 作者单位： | 东南大学,国家专用集成电路系统工程技术研究中心,江苏,南京,210096 |
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| 基金项目： | 高等学校博士学科点专项科研基金资助课题(20050286040) |
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| 摘 要： | I2C总线是飞利浦公司在1992年推出的芯片间互连的双向串行总线标准,与传统的并行连接相比,他具有只需要2根连接线,使用统一的串行协议来实现寻址与数据传递。I2C总线收发器的难点主要在于低噪声、低功耗和标准兼容性,本文描述了I2C总线收发器的设计,包括电路设计、版图设计以及模拟结果。Spice仿真结果表明该总线收发器达到了I2C标准要求。
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| 关 键 词： | I~2C 线与 收发器 I/O |
| 文章编号： | 1004-373X（2006）19-037-03 |
| 收稿时间： | 2006-04-16 |
| 修稿时间： | 2006年4月16日 |
Fast Mode I2C Bus Receiver Design |
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| YAN Jun,MA Jun.Fast Mode I2C Bus Receiver Design[J].Modern Electronic Technique,2006,29(19):37-39. |
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| Authors: | YAN Jun MA Jun |
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| Institution: | National ACIS System Engineering Research Center,Southeast University,Nanjing,210096,China |
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| Abstract: | I~2C bus is developed for interconnection between various chips in 1992.Compared with parallel interconnection,it has several advantages:only need two wires,uniform serial protocol for address and data.It is difficult to design a low power,low noise I~2C receiver.A fast mode I~2C bus receiver is designed in this article,which including circuit design,layout and simulation results.Simulation results with Spice demonstrate that it is compliant with I~2C fast mode standard. |
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| Keywords: | I~2C wired-and receiver I/O |
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