| 基于FPGA的永磁同步电机控制器设计 |
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| 引用本文： | 陈平,曾岳南,杨志平.基于FPGA的永磁同步电机控制器设计[J].国外电子元器件,2009(12):82-84. |
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| 作者姓名： | 陈平 曾岳南 杨志平 |
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| 作者单位： | 广东工业大学模式识别实验室; |
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| 摘 要： | 提出一种基于FPGA的永磁同步电机控制器的设计方案．该设计可应用于具有高动态性能要求的永磁同步电机伺服控制系统。为提高伺服控制系统的实时性，简化电路及节省成本，该系统设计采用Ahera公司生产的CycloneⅢ EP3C25Q240C8型FPGA器件实现电机控制器。嵌入NiosⅡCPU软核配合片内硬件乘法器及可编程逻辑门阵列，实现软硬件协同工作。通过QuartusⅡ软件自带的SignalTapⅡ嵌入式逻辑分析仪进行板上调试验证。得到带有死区输出的PWM波形。该PWM波形可用于电机驱动。
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| 关 键 词： | 同步电机控制 FPGA NiosⅡ SignalTapⅡ |
Design of PMSM controller based on FPGA |
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| CHEN Ping,ZENG Yue-nan,YANG Zhi-ping.Design of PMSM controller based on FPGA[J].International Electronic Elements,2009(12):82-84. |
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| Authors: | CHEN Ping ZENG Yue-nan YANG Zhi-ping |
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| Institution: | CHEN Ping,ZENG Yue-nan,YANG Zhi-ping(Lab of Pattern Recognition,Guangdong University of Technology,Guangzhou 510006,China) |
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| Abstract: | The design of PMSM controller based on FPGA is presented in this paper.This design is applied in the PMSM servo-control system requiring high dynamic performance.To improve the system real-time performance, simplify the circuit and save cost,Cyclone Ⅲ EP3C25Q240C8 ,which is Ahera FPGA chip,is used as the motor control chip.In this chip,the Nios Ⅱ soft core is embedded and works with embedded hardware multipliers and programmable logic elements.The structure based on software and hardware cooperation is implemented.Finally the chip is verified and tested by SignalTap Ⅱ embedded logic analysis in Quartus Ⅱ .The result presents that PWM waves with deadtime are generated.And these PWM waves are used to drive the motor. |
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| Keywords: | PMSM control FPGA Nios Ⅱ SignalTap Ⅱ |
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