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Search heuristics for a flowshop scheduling problem in a printed circuit board assembly process
Affiliation:1. Departament de Matemàtiques, Universitat Jaume I, Campus de Riu Sec, E-12071, Castelló de la Plana, Spain;2. Departamento de Matemáticas, Universidad de Murcia, Campus Espinardo, 30100 Murcia, Spain;3. Departamento de Análisis Matemático, Apartado de Correos 1160, Sevilla, 41080, Spain
Abstract:We consider a scheduling problem in a factory producing printed circuit boards (PCBs). The PCB assembly process in this factory can be regarded as a flowshop which has two special characteristics: jobs have sequence dependent setup times and each job consists of a lot (batch) of identical PCBs. Because of the latter characteristic, it is possible to start a job on a following machine before the job is entirely completed on a previous machine, that is, there is time-lag between machines. In this paper, we propose several heuristics, including taboo search (TS) and simulated annealing (SA) methods, for this generalized flowshop scheduling problem with the objective of minimizing mean tardiness. We compare suggested heuristics after series of tests to find appropriate values for parameters needed for the two search algorithms, TS and SA. Results of computational tests on randomly generated test problems are reported.
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