基于线计算的全加器设计

随着集成电路特征尺寸的不断缩小, 互连线在芯片内部占的比重越来越大, 但是互连线仅用于数据传输, 芯片计算能力仍然需要依靠晶体管开关实现. 如何在有限的硬件资源内进一步提高芯片的计算能力, 已经成为当前集成电路设计的核心问题. 本文通过研究金属互连线间电容耦合效应, 采用互连线串扰现象完成逻辑运算的思想, 提出一种基于线计算的全加器设计方案. 该方案首先建立线计算模型, 通过调整反相器阈值和不同干扰线与受扰线之间电容耦合强度匹配技术, 采用相同线计算电路结构实现不同功能的逻辑门电路; 然后, 在逻辑门的基础上实现基于线计算的全加器; 最后, 在TSMC 65nm CMOS工艺下仿真验证. 结果表明, 所设计的线计算电路具有正确逻辑功能, 与传统设计方法相比, 线计算逻辑门具有更低开销, 且线计算电路具有抗逆向工程能力.

Design of full adder based on line crosstalk computing

With the on-going reduction of the characteristic size of integrated circuits, the interconnected metal wires take up an increasing proportion in the chip space. However, these wires are only used for data transmission, and the chip’s computing ability still depends on the switch of transistors. How to improve the computing ability of chip with limited hardware resources has become a key issue of IC design. In this paper, by studying the capacitive coupling effect resulting from the metal interconnectors and the advantage of using the line crosstalk phenomenon to complete the logical operation, a design scheme of full adder based on line crosstalk computing is proposed. The scheme first establishes a line crosstalk computing model, and uses the same line crosstalk computing circuit structure to implement different logic gates by adjusting the inverter threshold and the capacitive coupling strength between different interference lines and the victim line. Then, a full adder based on line crosstalk computing is implemented on the basis of logic gates. Finally, the simulation verification under the TSMC 65nm CMOS process shows that the designed line crosstalk computing circuit has the correct logic function. Compared with traditional design methods, the line crosstalk computing logic gates achieve lower overhead, and the line crosstalk computing full adder acquires the ability to resist reverse engineering scheme.