| 一种改进的汉明码译码器设计与FPGA验证 |
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| 引用本文： | 田凯.一种改进的汉明码译码器设计与FPGA验证[J].电视技术,2013,37(17). |
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| 作者姓名： | 田凯 |
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| 作者单位： | 重庆邮电大学光纤通信技术重点实验室,重庆,400065 |
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| 基金项目： | 国家自然科学基金项目（面上项目，重点项目，重大项目） |
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| 摘 要： | 提出了一种汉明码译码器改进方法,采用串行数据传输和时序优化的方法来降低汉明码译码器占用的资源和成本,并采用模块式的设计方法,设计了编译码系统仿真平台,详细地阐述了整个系统和各个模块的FPGA实现过程.仿真结果表明,设计的译码器复杂度明显降低.
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| 关 键 词： | 汉明码 译码器 串行数据传输 时序优化 FPGA |
| 收稿时间： | 2012/12/10 0:00:00 |
| 修稿时间： | 2013/3/15 0:00:00 |
An Improved Design of Hamming Code Decoder and FPGA Verification |
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| tiankai.An Improved Design of Hamming Code Decoder and FPGA Verification[J].Tv Engineering,2013,37(17). |
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| Authors: | tiankai |
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| Institution: | Chongqing University of Posts and Telecommunications |
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| Abstract: | An improved method for improving Hamming code decoder is proposed. And a method of serial data transmission and timing optimization is devised to reduce the occupied resource and cost of Hamming decoder. This paper also presents a modular design which is used to design the simulation platform of encoded and decoded system. FPGA implementation process of the entire system and the individual module is detailed described. Simulation results show that the complexity of designed decoder is significantly reduced. |
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| Keywords: | Hamming code decoder serial data transmission timing optimization FPGA |
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