高速Viterbi译码器中加-比-选单元的设计与实现

限制高速Vitefibi译码实现的“瓶颈”为具有非线性反馈特征的“加-比-选”单元。文献3]在分析“加-比-选”运算代数结构的基础上提出了M步“加-比-选”算法。本文进一步发掘了该算法的并行性，并利用FPGA内寄存器资源丰富的特点，在Xilink的FPGA上采用流水线结构实现了基于M步“加-比-选”算法的“加-比-选”单元。仿真结果表明，该方案有效地克服了传统“加-比-选”单元的“瓶颈”效应，极大地提高了Viterbi译码器的译码速率。

Design and implementation of add-compare-select unit in high speed Viterbi decoder

The bottleneck for a high-speed Viterbi decoder implementation is add-compare-select unit which contains a nonlinear feedback loop.By analyzing the algebraic structure of add-compare-select operation, the literatur3] presented a M-step add-compare-select algorithm.Our paper presents the parallelism of the algorithm in a further way,and with the characteristic that FPGA is rich in registers we design a add-compare-select unit with pipeline structure on FPGA of Xilink.Simulation results prove that the scheme presented here breaks the bottleneck of conventional add-compare-select unit,which improves the speed of Vi-(terbi) decoder greatly.