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高重频束流采集处理器原型样机的设计
引用本文:田丰收,赵雷,范怡淳,秦家军,赖龙伟,刘树彬,安琪.高重频束流采集处理器原型样机的设计[J].原子核物理评论,2021,38(4):402-409.
作者姓名:田丰收  赵雷  范怡淳  秦家军  赖龙伟  刘树彬  安琪
作者单位:1.核探测与核电子学国家重点实验室,中国科学技术大学,合肥 230026
基金项目:中国科学院知识创新工程重要方向性项目(KJCX2-YW-N27); 中国科学院青年创新促进会
摘    要:为了实现对高重频硬X射线自由电子激光装置(SHINE)条带型BPM(Beam Position Monitor)系统信号的数字化采样和处理,研制了高重频束流采集处理器原型样机。处理器拥有四通道输入,最高达1 GSps的采样率,16 bit采样位数,采用XILINX公司带有嵌入式CPU(Central Processing Unit)的ZYNQ系列FPGA(Field Programmable Gate Array),可以运行Linux系统,同时可以实现高速采样数据的缓存与读出。处理器采用子母板结构设计,子板为ADC(Analog To Digital Converter)采样板,母板为FPGA数字处理板,子母板通过FMC(FPGA Mezzanine Card)接口进行数据传输。ADC采用JESD204B协议进行数据传输,子母板间通过16对差分信号连接通道,最大总传输速率达到80 Gbps。ADC采样数据传入数字母板后,经过FIFO和DDR的缓存,最后通过TCP/IP协议由RJ45接口传输到上位机进行处理和分析,RJ45接口的数据传输速率约为900 Mbps。经过测试,ADC采集子板的带宽高于480 MHz,且在480 MHz带宽内有效位高于10位。FPGA数字母板运行经Petalinux编译的Linux系统,可以实现对连续或者触发模式下,四通道一百万个采样点的存储与数据传输。整个设计可以满足设计要求。

关 键 词:SHINE    ZYNQ    高速数据采集    波形数字化
收稿时间:2021-03-08

Design of High-repetition-rate Beam Sampling Processor Prototype
Fengshou TIAN,Lei ZHAO,Yichun FAN,Jiajun QIN,Longwei LAI,Shubin LIU,Qi AN.Design of High-repetition-rate Beam Sampling Processor Prototype[J].Nuclear Physics Review,2021,38(4):402-409.
Authors:Fengshou TIAN  Lei ZHAO  Yichun FAN  Jiajun QIN  Longwei LAI  Shubin LIU  Qi AN
Institution:1.State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei 230026, China2.Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China3.Shanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201204, China
Abstract:In order to sample and process the signal of the Shanghai High Repetition Rate XFEL and Extreme Light Facility (SHINE) strip-line BPM system, a prototype of High-Repetition-Rate Beam Sampling Processor was developed. The processor has four channel input, 1 GSps maximum sampling rate and 16 bit resolution. It adopts Xilinx Zynq series FPGA with embedded ARM core, which can run Linux operating system and realize readout of high-speed sampled-data and data buffering. The processor adopts the structure of mother board and daughter board. The daughter board with ADC is for data sampling, and the mother board with FPGA is used to process the digital data. The daughter board and the mother board transmit data through the FMC interface. The ADC uses JESD204B protocol to transmit data, and the maximum total data rate is 80 Gbps through 16 pairs of differential channels. First the ADC data is transmitted to the digital motherboard. Then it is buffered by FIFO and DDR and finally transmitted to the upper computer for processing and analysis through the RJ45 interface with TCP/IP protocol. The data rate of RJ45 interface is about 900 Mbps. After testing, the bandwidth of ADC daughter board is higher than 480 MHz, and the ENOB(effective number of bits) is higher than 10-bit in 480 MHz bandwidth. The FPGA digital mother board runs Linux compiled by Petalinux, which can realize the data storage and transmission of 1 M sampling points of four channels in continuous or trigger mode. The processor can meet the design requirements.
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