Failure probability estimation with differently sized reference products for semiconductor burn‐in studies

A burn‐in study is applied to demonstrate compliance with a targeted early life failure probability of semiconductor products. This is achieved by investigating a sample of the produced chips for reliability‐relevant failures. Usually, a burn‐in study is carried out for a specific reference product with the aim to scale the reference product's failure probability to follower products with different chip sizes. It also appears, however, that there are multiple, differently sized reference products for which burn‐in studies are performed. In this paper, we present a novel model for estimating the failure probability of a chip, which is capable of handling burn‐in studies on multiple reference products. We discuss the model from a combinatorial and a Bayesian perspective; both approaches are shown to provide more accurate estimation results in comparison with a simple area‐based approach. Moreover, we discuss the required modifications of the model if the observed failures are tackled by countermeasures implemented in the chip production process. Finally, the model is applied to the problem of determining the failure probabilities of follower products on the basis of multiple reference products.