| 一种HIMAC硬件协处理器的设计与FPGA实现 |
| |
| 引用本文： | 潘伟涛,邱智亮.一种HIMAC硬件协处理器的设计与FPGA实现[J].电子器件,2012,35(2):221-226. |
| |
| 作者姓名： | 潘伟涛 邱智亮 |
| |
| 作者单位： | 西安电子科技大学综合业务网理论及关键技术国家重点实验室,西安,710071 |
| |
| 基金项目： | 国家“863”项目(KJ0300102902);国家“863”计划项目(2011AA01A106);核高基项目(KJ0800112902);中央高校基本科研业务费专项资金(K50511010017) |
| |
| 摘 要： | 为降低HINOC系统中CPU负荷,设计了一种HINOC MAC层的硬件加速协处理器,将部分软件功能采用硬件实现。设计采用硬件流分类机制及基于定长单元存储变长分组的队列管理方法,实现了各种业务流的快速分组、转发、调度等性能的明显提升。该设计通过了仿真及FPGA验证,实现了CPU、HIPHY及以太网之间数据的快速搬移处理。
|
| 关 键 词： | 嵌入式系统 HIMAC FPGA 逻辑综合 |
FPGA-based Design for a HIMAC Coprocessor |
| |
| PAN Weitao
,
QIU Zhiliang.FPGA-based Design for a HIMAC Coprocessor[J].Journal of Electron Devices,2012,35(2):221-226. |
| |
| Authors: | PAN Weitao QIU Zhiliang |
| |
| Institution: | *(State Key Laboratory of Integrated Services Networks,Xidian Univ.,Xi ’ an 710071,China) |
| |
| Abstract: | In order to reduce the load of CPU in HINOC system,a hardware acceleration coprocessor is presented based on MAC protocol of HINOC,and part of the software function has been realized by hardware.The hardware flow classification mechanism and the queue management method in which store variable length packet based on fixed length unit are used in design,and the functions of grouping,forwarding and scheduling for different business flow have been improved significantly.The design,which has been simulated and verified in FPGA,realizes fast data transmission between CPU、HIPHY and ethernet. |
| |
| Keywords: | embedded system HIMAC FPGA logic synthesis |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
| 点击此处可从《电子器件》浏览原始摘要信息 |
| 点击此处可从《电子器件》下载免费的PDF全文 |
|
