硬件电路的选择性进化冗余

提出了一种新的冗余容错电路设计方法.首先利用遗传算法生成多个功能相同但结构不同的电路,这些电路在相同的出错条件下同时出错的概率较小;然后对生成的多个电路进行选择性集成,使集成后电路尽可能有利于投票表决,从而提高容错性能.对传统的同构冗余电路与异构冗余电路的容错能力进行了理论分析和对比,并给出了冗余电路的选择策略.实验结果表明,异构冗余电路比同构冗余电路具有更好的容错特性,且选择性冗余比随机冗余更优.

Selective redundancy of evolved circuits

A new design method of redundant fault-tolerant circuits was proposed. Firstly, genetic algorithm was used to generate many circuits with the same function but different structure. These circuits have low probability of being faulty simultaneously under the same circumstance. Then some of these circuits were selectively ensembled to be a redundant circuit, which was propitious to voting. And fault-tolerant performance was improved accordingly. The fault-tolerant performance of same-structure and different structure redundant circuits were analyzed and compared, and that the selective strategy of redundant circuit was also proposed. The experimental results prove that redundant circuits of different structure have better fault-tolerant performance and that the selective redundancy is better than random redundancy.