基于P掺杂SiO2为栅介质的超低压侧栅薄膜晶体管

在室温下利用等离子体增强化学气相沉积法(PECVD)制备的颗粒膜P掺杂SiO₂为栅介质, 使用磁控溅射方法利用一步掩模法制备出一种新型结构的侧栅薄膜晶体管. 由于侧栅薄膜晶体管具有独特的结构, 在射频磁控溅射过程中, 仅仅利用一块镍掩模板, 无需复杂的光刻步骤, 就可同时沉积出氧化铟锡(ITO)源、漏、栅电极和沟道, 因此, 这种方法极大地简化了制备流程, 降低了工艺成本. 实验结果表明, 在P掺杂SiO₂栅介质层与沟道层界面处形成了超大的双电层电容(8 μF/cm²), 这使得这类晶体管具有超低的工作电压1 V, 小的亚阈值摆幅82 mV/dec、高的迁移率18.35 cm²/V·s和大的开关电流比1.1×10⁶. 因此, 这种P掺杂SiO₂双电层超低压薄膜晶体管将有望应用于低能耗便携式电子产品以及新型传感器领域. 关键词： 2')" href="#">P掺杂SiO₂ 侧栅薄膜晶体管 双电层(EDL) 超低压

Ultralow-voltage in-plane-gate indium-tin-oxide thin-film transistors made of P-doped SiO2 dielectrics

A new kind of indium-tin-oxide thin-film transistors made of P-doped SiO₂ dielectrics in an in-plane-gate structure is fabricated at room temperature. Indium-tin-oxide (ITO) channel and ITO electrodes (gate, source, and drain) can be deposited simultaneously without precise photolithography and alignment process by using only one nickel shadow mask. So the thin film transistors (TFTs) have a lot of advantages, such as the simple device process、low cost etc. Such TFTs exhibit a good performance at an ultralow operation voltage of 1 V, a high field-effect mobility of 18.35 cm²/Vs , a small subthreshold swing of 82 mV/decade, and a large on-off ratio of 1.1×10⁶, because of the huge electric-double-layer (EDL) capacitance (8 μF/cm²) between the interface of P-doped SiO₂ dielectrics and ITO channel. So the TFTs are very promising for the application of low-power and portable electronic products and sensors in the future.
Keywords： 2 dielectric')" href="#">P-doped SiO₂ dielectric in-plane-gate thin-film transistors electric-double-layer (EDL) ultralow operation voltage