Abstract: | A newly designed sample-and-hold(S/H) integrated circuit based on the 1.5 micron N-well CMOS technology for 8-bit high-speed analog to digital converter is described. It can realize the 40-MHz sampling rate and 8-bit resolution. The good performance of S/H circuit benefits from the use of a newly designed regulated cascode operator amplifier, which has a DC gain of 140-dB, unity-gain bandwidth of 407-MHz, phase margin of 53 degree and power consumption of 90mW. It is superior to the operator amplifier of 60-dB, 107-MHz, 13 degree, and 33mW respectively, which is used in the similar S/H circuit based on the 0. 8 micron technology and designed by Michio Yotsuyanagi. |