| Numerical Study on a Lateral Double-Gate Tunnelling Field Effect Transistor |
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| 作者姓名： | 何进 边伟 陶亚东 刘峰 宋岩 张兴 |
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| 作者单位： | [1]Shenzhen Graduate School, Peking University, Senzhen, 518055 [2]Multi-Project-Wafer （MPW） Center, Institute of Microelectronics, School of Electroni;VEngineering and Computer Science, Peking University, Beijing 100871 |
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| 基金项目： | Supported by the National Bazic Research Program of China under Grant No 2006CB302704, and the National Natural Science Foundation of China under Grant No 90607017. |
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| 摘 要： | A novel lateral double-gate tunnelling field effect transistor （DG-TFET） is studied and its performance is presented by a two-dimensional device simulation with code ISE. The result demonstrates that this new tunnelling transistor allows for the steeper sub-threshold swing below 60mV/dec, the super low supply voltage （operable at VDD 〈 0.3 V） and the rail-to-rail logic （significant on-state current at the drain-source voltage VDS = 50mV） for the aggressive technology assumptions of the availability of high-k/metal stack with equivalent gate oxide thickness EOT =0.24 nm and the work function difference 4.5 eV of materials.
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| 关 键 词： | 侧向多门 穿隧式场效应晶体管 数值模拟 输出特性 |
| 收稿时间： | 2006-03-25 |
| 修稿时间： | 2006-03-25 |
Numerical Study on a Lateral Double-Gate Tunnelling Field Effect Transistor |
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| HE Jin,BIAN Wei,TAO Ya-Dong,LIU Feng,SONG Yan,ZHANG Xing.Numerical Study on a Lateral Double-Gate Tunnelling Field Effect Transistor[J].Chinese Physics Letters,2006,23(12):3373-3375. |
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| Authors: | HE Jin BIAN Wei TAO Ya-Dong LIU Feng SONG Yan ZHANG Xing |
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| Institution: | 1.Shenzhen Graduate School, Peking University, Senzhen, 518055 ;2.Multi-Project-Wafer (MPW |
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| Abstract: | A novel lateral double-gate tunnelling field effect transistor (DG-TFET) is studied and its performance is presented by a two-dimensional device simulation with code ISE. The result demonstrates that this new tunnelling transistor allows for the steeper sub-threshold swing below 60 mV/dec, the super low supply voltage (operable at VDD<0.3 V) and the rail-to-rail logic (significant on-state current at the drain-source voltage VDS=50 mV) for the aggressive technology assumptions of the availability of high-k/metal stack with equivalent gate oxide thickness EOT=0.24 nm and the work function difference 4.5 eV of materials. |
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| Keywords: | 85 30 Mn 85 30 Tv 85 30 -p |
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