| 600 V高低压兼容BCD工艺及驱动电路设计 |
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| 引用本文： | 蒋红利,朱玮,李影,乔明. 600 V高低压兼容BCD工艺及驱动电路设计[J]. 微电子学, 2010, 40(1) |
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| 作者姓名： | 蒋红利 朱玮 李影 乔明 |
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| 作者单位： | 1. 中国电子科技集团公司,第五十八研究所,江苏,无锡,214035
2. 电子科技大学,薄膜与集成器件国家重点实验室,成都,610054 |
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| 基金项目： | 中国电子科技集团公司预研支撑项目(62501080405);;江苏省工业支撑项目(BE2008010) |
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| 摘 要： | 基于高压功率集成电路的关键参数性能要求和现有工艺条件,在国内3μmCMOS工艺基础上,开发出8～9μm薄外延上的600VLDMOS器件及高低压兼容BCD工艺,并设计出几款600V高压半桥栅驱动电路。该工艺在标准3μm工艺基础上增加N埋层、P埋层及P-top层,P埋层和P阱对通隔离,形成各自独立的N-外延岛。实验测试结果表明:LDMOS管耐压达680V以上,低压NMOS、PMOS及NPN器件绝对耐压达36V以上,稳压二极管稳压值为5.3V。按该工艺进行设计流片的电路整体参数性能满足应用要求,浮动偏置电压达780V以上。
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| 关 键 词： | 高压半桥栅驱动电路 高低压兼容BCD工艺 双RESURF LDMOS |
A 600 V High/Low Voltage Integrated BCD Process and Drive Circuit Design |
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| JIANG Hongli,ZHU Wei,LI Ying,QIAO Ming. A 600 V High/Low Voltage Integrated BCD Process and Drive Circuit Design[J]. Microelectronics, 2010, 40(1) |
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| Authors: | JIANG Hongli ZHU Wei LI Ying QIAO Ming |
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| Affiliation: | 1.The 58th Research Institute/a>;China Electronics Technology Group Corporation/a>;Wuxi/a>;Jiangsu 214035/a>;P.R.China/a>;2.State Key Lab of Elec.Thin Films and Integr.Dev./a>;Univ.of Elec.Sci.and Technol.of China/a>;Chengdu 610054/a>;P.R.China |
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| Abstract: | Based on key parameters of high voltage IC and the current process condition, a 600 V high/low voltage BCD process using 8-9 μm thin epitaxial layer was developed based on a 3 μm CMOS process. In this process, N-bury, P-bury and P-top layers were added, and P-well was used as down diffusion to form N-type epitaxial island with P-bury. Test results showed that the double RESURF LDMOS had a breakdown voltage above 680 V, while the low voltage NMOS/PMOS/NPN had a breakdown voltage above 36 V, and the Zener diode had a limited voltage of 5.3 V. An HVIC was designed and fabricated based on the process. The specification and performance of the circuit, which had a floating bias voltage beyond 780 V, meet the requirements for application. |
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| Keywords: | High voltage half-bridge driver High/low voltage integrated BCD process Double RESURF LDMOS |
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