| 安全散列算法的FPGA实现与仿真 |
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| 引用本文： | 崔东岳,龙兵,曾浩,向川云.安全散列算法的FPGA实现与仿真[J].电子质量,2010(12):19-21,28. |
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| 作者姓名： | 崔东岳 龙兵 曾浩 向川云 |
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| 作者单位： | 电子科技大学自动化工程学院,四川,成都,611731 |
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| 摘 要： | 安全散列算法是一种常用的加密算法,在信息安全领域得到了广泛应用。该文通过设计硬件电路,建立SHA-1算法的模型并实现。在FPGA中实现SHA-1算法时采取并行处理的方法,对算法的实现流程进行了优化,通过模块化设计,缩短了算法实现的周期,减少了存储资源的占用。最后进行综合和仿真,验证了算法实现的正确性。
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| 关 键 词： | 现场可编程逻辑门阵列 安全散列算法 硬件描述语言 |
Implementation and Simulation of SHA-1 Algorithm Based on FPGA |
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| Cui Dong-yue,Long Bing,Zeng Hao,Xiang Chuan-yun.Implementation and Simulation of SHA-1 Algorithm Based on FPGA[J].Electronics Quality,2010(12):19-21,28. |
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| Authors: | Cui Dong-yue Long Bing Zeng Hao Xiang Chuan-yun |
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| Institution: | Cui Dong-yue,Long Bing,Zeng Hao,Xiang Chuan-yun(School of Automation Engineering,UESTC,Sichuan Chengdu 611731) |
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| Abstract: | Secure Hash Algorithm is one of the most common encryption algorithms,it is widely used in information security field.In this article,we build SHA-1 algorithm model and implement through hardware design.Using parallel processing method to implement the SHA-1 based on FPGA,it shortens the implement time,reduces the occupancy of storage resource.And we simulate and synthesis the algorithm,verify the correctness of the implementation. |
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| Keywords: | FPGA SHA Algorithm Verilog HDL |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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