GaN/SiC异质结的慢正电子研究

通过对不同生长厚度GaN/SiC(n-n)的慢正电子研究，发现在GaN/SiC的界面中存在大量各种缺陷并在界面两端形成两个不同方向的电场. 这些缺陷的产生和SiC衬底表面制备以及GaN和SiC不同的热膨胀系数有关. 而缺陷中大量的带状缺陷在界面中形成一个费米能级钉扎(Fermi level pinning),它的存在使界面中存在一定高度的势垒，导致在界面两端的一定区域内形成两个不同方向的电场. 用VEPFIT模拟该电场的存在，分四层(GaN/Interface/SiC1/SiC2)进行拟合,得到了很好的拟 关键词： 正电子湮没 缺陷 半导体

Study of GaN/SiC contact using slow positron beam

Using a slow positron beam and the program VEPFIT, we found there exists a barrier in the interface between GaN and SiC, which is caused by lots of band-like defects existing in it. The existence of the barrier induced two backing electric fields in diverse directions close to the interface. These fields can produce a longer diffusion length in the SiC region where no field exists compared with that of SiC region, which has an electric field at a set value. The fitted value of the electric field offers a good reference for studying the situation in a real the interface.