Surface passivation technology for III-V semiconductor nanoelectronics |
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Authors: | Hideki Hasegawa Masamichi Akazawa |
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Affiliation: | Research Center for Integrated Quantum Electronics (RCIQE) and Graduate School of Information Science and Technology, Hokkaido University, N-13, W-8, Kita-ku, Sapporo 060-8628, Japan |
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Abstract: | The present status and key issues of surface passivation technology for III-V surfaces are discussed in view of applications to emerging novel III-V nanoelectronics. First, necessities of passivation and currently available surface passivation technologies for GaAs, InGaAs and AlGaAs are reviewed. Then, the principle of the Si interface control layer (ICL)-based passivation scheme by the authors’ group is introduced and its basic characterization is presented. Ths Si ICL is a molecular beam epitaxy (MBE)-grown ultrathin Si layer inserted between III-V semiconductor and passivation dielectric. Finally, applications of the Si ICL method to passivation of GaAs nanowires and GaAs nanowire transistors and to realization of pinning-free high-k dielectric/GaAs MOS gate stacks are presented. |
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Keywords: | 71.20.Nr 71.55.Eq 73.21.Hb 73.40.Gk 73.40.Kp |
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