Electrical characterization of high-k gate dielectrics on semiconductors |
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Authors: | T.P. Ma |
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Affiliation: | Department of Electrical Engineering, Yale University, New Haven, CT 06520-8284, United States |
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Abstract: | This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks: (1) inelastic electron tunneling spectroscopy (IETS), (2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of a MOSFET, and (3) pulse agitated substrate hot electron injection (PASHEI) technique for measuring trapping effects in the gate dielectric at low and modest gate voltages. |
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Keywords: | Electrical characterization High-k dielectrics Semiconductors MOSFET IETS Charge pumping Lateral profiling |
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