超深亚微米可制造标准单元库设计

当集成电路的特征尺寸下降到100nm以下,可制造性设计就变得尤为重要。本文提出了一种65nm可制造性标准单元库的设计方法。通过精简基本单元的数量,降低光学矫正的时间和空间复杂度；利用DFM设计规则和光学模拟仿真对每个单元的版图进行优化以提高整个单元库的可制造性。应用该方法实现的标准单元库在时序,功耗,面积方面与传统标准单元库相比具有很好的性能,并且通过Foundry的TD部门65nm工艺线的可制造性测试,有利于65nm工艺生产良率的提升。

Design for manufacturability of a VDSM standard cell library

This paper presents a method of designing a 65 nm DFM standard cell library. By reducing the amount of the library largely, the process of optical proximity correction (OPC) becomes more efficient and the need for large storage is reduced. This library is more manufacture-friendly as each cell has been optimized according to the DFM rule and optical simulation. The area penalty is minor compared with traditional library, and the timing, as well as power has a good performance. Furthermore, this library has passed the test from the Technology Design Department of Foundry. The result shows this DFM standard cell library has advantages that improve the yield.