10bit 100M低功耗时间交织运放共享模数转换器设计

本文设计了一个应用于3G接收机中频的10比特100兆采样率的双通道时间交织流水线模数转换器，为了降低功耗，运放在两通道间共享。针对通道间的直流失调失配，增益失配以及采样时间偏差，设计分别采用共享运放，增加每个通道转换精度以及全局采样技术来加以解决。通过改变时序，消除了输出开关电荷注入以及断开开关的电容造成的串扰，从而提高了整个模数转换器的线性度。整个模数转换器的供电电压为3.3V，功耗为70毫瓦，采用了180纳米CMOS工艺，面积为3×2mm2，在奈奎斯特频率以内，其杂散无失真动态范围大于70dB,其信杂比大于56dB。

A 10-bit 100-Msps low power time-interleaved ADC using OTA sharing

A high performance 10-bit 100-MS/s two-channel time-interleaved pipelined ADC is designed for intermediate frequency 3G receivers, and OTA is shared among the channels for low power dissipation. Offset mismatch, gain mismatch and time skew mismatch are overcome by OTA sharing, increasing the accuracy of each channel and global passive sampling respectively. The linearity deterioration caused by the charge injection of the output switch and the crosstalk of the off-switch capacitor is removed by modifying the clock signal arrangement. The total power consumption of the presented ADC is 70 mW from a 3.3-V power supply. Fabricated in a 180-nm CMOS process, the core of the prototype occupies an area of 2.5 × 1.5 mm², achieving more than 70-dB spurious-free dynamic range and over 56-dB signal-to-noise distortion ratio over the Nyquist input band at 100-MHz sampling frequency.