| 基于SystemVerilog的I^2C总线模块验证 |
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| 引用本文： | 闫涛,申志飞,易茂祥,梅春雷.基于SystemVerilog的I^2C总线模块验证[J].电子科技,2011,24(12):35-37. |
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| 作者姓名： | 闫涛 申志飞 易茂祥 梅春雷 |
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| 作者单位： | (合肥工业大学 电子科学与应用物理学院,安徽 合肥 230009) |
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| 基金项目： | 安徽省教育厅自然科学重点基金资助项目 |
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| 摘 要： | 针对I2C总线模块,介绍了一种基于Systemverilog验证环境的验证IP设计。这种基于面向对象设计的验证架构可以很容易地被重用。文中分析了基于Systemverilog验证环境的结构,并在介绍I2C总线协议的基础上,重点论述了验证环境中事务产生器及驱动器的设计
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| 关 键 词： | Systemverilog I^2C总线 事务产生器 事务驱动器 |
Verification of I^2C Bus Model Using SystemVerilog |
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| YAN Tao,SHEN Zhifei,YI Maoxiang,MEI Chunlei.Verification of I^2C Bus Model Using SystemVerilog[J].Electronic Science and Technology,2011,24(12):35-37. |
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| Authors: | YAN Tao SHEN Zhifei YI Maoxiang MEI Chunlei |
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| Institution: | (School of Electronic Science and Applied Physics,Hefei University of Technology,Hefei 230009,China) |
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| Abstract: | A design for IP verification of I2C bus module based on Systemverilog is introduced.The verification design based on the object-oriented method can be easily reused.The structure of Systemverilog is analyzed and I2C bus protocol is introduced.After that,the paper focuses on the design of the affair generator and drive in the verification environment |
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| Keywords: | systemverilog I^2 C bus generation drive |
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