Fabrication of silicon webs in the decananometre range

In addition to the high demands on lithography, short-channel effects are problems for miniaturisation of devices. Double-gate MOSFETs are known to improve the short-channel behaviour and are traded in the ITRS roadmap as a part of non-classical CMOS, which can provide a path to scaling MOSFETs below the 65-nm node. For the centre of a special vertical layout a silicon web with 300-nm height and 20-nm width is required. The web lines are made by electron-beam lithography with hydrogen silsesquioxane (HSQ) as negative tone resist. 23-nm wide and 100-nm high lines in HSQ were attained. The transfer of the structures to a substrate by dry etching results in 30-nm-wide and 300-nm-high silicon lines. PACS 81.16.Nd; 81.16.Rf; 85.30.Tv