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Shrinking limits of silicon MOSFETs: numerical study of 10 nm scale devices
Institution:1. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USA;2. Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Republic of Korea;1. Department of Engineering Physics, Polytechnique de Montréal, P.O. Box 6079, Station Centre-ville, Montréal, Canada;2. Department of Electrical Engineering, Polytechnique de Montréal, P.O. Box 6079, Station Centre-ville, Montréal, Canada
Abstract:We have performed numerical modeling of dual-gate ballistic n-MOSFETs with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a self-consistent solution of the full (two-dimensional) electrostatic problem, with account of electric field penetration into the heavily doped electrodes. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4000 mS mm ? 1or gate modulation of current by more than 8 orders of magnitude, depending on the gate oxide thickness. These characteristics make the devices satisfactory for logic and memory applications, respectively, although their gate threshold voltage is rather sensitive to nanometer-scale variations in the channel length.
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