Performance limits of CMOS technology and perspectives of quantum devices |
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| Institution: | 1. Université de Lorraine, CRAN, UMR 7039, 2 avenue de la Forêt de Haye, 54516 Vandœuvre-lès-Nancy, France;2. CNRS, CRAN, UMR 7039, 54516 Vandœuvre-lès-Nancy, France;1. FEMTO-ST Institute/CNRS, University Bourgogne Franche-Comté, Belfort, France;2. Claude Bernard Lyon 1 University, Lyon, France;1. IMEC, Kapeldreef 75, Leuven 3001, Belgium;2. Quantum Solid State Physics, KU Leuven, Celestijnenlaan 200D, Leuven 3001, Belgium;3. Ion Beam Centre, University of Surrey, Guildford, Surrey GU2 7XH, United Kingdom |
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| Abstract: | In this work we examine the performance limits of CMOS technology in the nanometer regime. The starting point of our discussion is the 1999 International Technology Roadmap for Semiconductors, which represents the current view of Industry on the future evolution and prospects of microelectronics. Next, we shortly address the physical principles of single-electron devices, and speculate on the opportunities offered by them for the implementation of single-electron circuits for logic and memory applications. |
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