关于主流BITS设备技术性能监测问题的研究

针对目前通信业内主流数字同步设备(SYNLOCK-V3)的实际运用情况，根据大量性能测试及调查研究结果，分析了其频偏检测机制、FREQ告警门限值、MTIE、TDEV模板设定、频率牵引范围等多个技术设计问题，或与业内通行标准值具有较大的差距。指出该类问题有关的不利影响:必然会导致当同步性能劣化时，不能及时有效告警，严重影响整个同步网络运用的同步性能质量，并使维护人员误认为性能达标而不能及时发现和处理问题。在此基础上提出了改进建议。

Research on the technology mainstream BITS equipment performance monitoring issues

The actual use for the current situation of the industry mainstream digital synchronous communication device (SYNLOCK-V3), according to the a large number of performance tests and the results of investigation, analyzed the frequency offset detection mechanism, FREQ alarm threshold, MTIE, TDEV template set , frequency pulling range and other technical design issues, or with prevailing industry standard values have a larger gap. He pointed out that the adverse effects related to this kind of problem: when the synchronization will inevitably lead to performance degradation, you can not timely and effective warning, seriously affecting the quality of the synchronization performance synchronous network utilization, and maintenance personnel can not be mistaken for performance standards and to discover and deal with the problem. On this basis, recommendations for improvements.